The present invention relates frequency synthesizers and direct modulation, more particularly to phase locked loops, and even more particularly to digital phase detectors for use in a phase locked loop.
Phase locked loops (PLLs) are well known, and are useful for generating oscillating signals in many types of circuits, including but not limited to radio circuitry. In digital communication systems, for example in mobile telephone communications operating under the GSM or DCS systems, PLLs may be employed to effect continuous phase modulation (CPM) of a carrier signal.
FIG. 1 is a block diagram of a conventional integer-divide PLL 100. A phase detector 101 compares the phase of a signal supplied by a reference oscillator 103 with the phase of a feedback signal supplied by a frequency divider 105. The output of the phase detector, which represents the phase difference between the two input signals, is filtered by a filter 107. The filtered output is then used to control the frequency of an output signal generated by a voltage controlled oscillator (VDO) 109. The output signal from the VCO 109, in addition to being supplied as an output from the PLL, is also supplied as an input to the frequency divider 105, and is thus the source of the feedback source. The PLL 100 is governed by the following equations:                                           i            e                    =                                    K              P                        ⁡                          (                                                ϕ                  R                                -                                                      ϕ                    o                                    N                                            )                                      ⁢                                  ⁢                                            ϕ              o                        =                                          i                e                            ⁢                              Z                ⁡                                  (                  s                  )                                            ⁢                                                K                  V                                s                                              ,                                    (        1        )            where s, Kp, Z(s), and KV are the complex frequency, phase detector gain, loop-filter trans-impedance, and VCO gain, respectively, and φR, φ0, and ie, are the reference phase (or frequency as 2πƒ=s*φ), the VCO phase, and the phase-determined error current, respectively.
Solving the above equations for φo yields the well-known result that θo=N·ƒR, that is, the VCO frequency is an integer multiple of the reference frequency.
Since the loop response time to a change in N (e.g., when a new channel is selected) is proportional to 1/ƒR (i.e., it takes a certain number of reference cycles to settle) and the minimum channel spacing equals ƒR, there is a conflict in the choice of reference frequency. That is, it would be desirable to set a low value for ƒR to reduce the minimum channel spacing. However, such a setting would result in a larger loop response time, which is undesirable.
To get around the above restriction on channel spacing, fractional-N PLLs have been devised. By employing a variable-modulus divider, rather than an integer divider, it is possible to achieve more flexible divide ratios. For example, performing three successive divisions by 20 followed by one division by 21 results in an average division factor of (3·20+21)/4=20.25 and a channel spacing of ƒR/4. Due to the repetitive nature of this variable modulus division, however, spurious tones will be generated (here at ƒo±n·ƒR) that will modulate the VCO.
Recently, ΔΣ modulators have been employed to shape the spurious response of the fractional-N divider. A graph depicting a typical ΔΣ noise density distribution is depicted in FIG. 2. The spurious tone is replaced by a spectrum of spurious tones with most of the spurious energy pushed out in frequency, well beyond the bandwidth of the PLL, essentially being centered around ƒR/2, where ƒR is the clocking rate of the ΔΣ modulator. A thermal noise floor (e.g., thermal noise attributable to the divider circuitry) is also included. As a result of the shaping performed by the ΔΣ modulator, this spurious energy will have a substantially reduced effect on the output signal from the PLL.
An exemplary embodiment of a ΔΣ fractional-N PLL 200 is depicted in FIG. 3. The phase detector 201, reference oscillator 203, filter 207 and VCO 209 are analogous to those counterpart elements described with respect to FIG. 1, and therefore need not be described here in detail. The frequency divider 205 in this case is capable of dividing by any integer modulus in the range N±M, and has two inputs: one for receiving a value for N, and another for receiving a value of M. By appropriately varying the value of M as described above, an effective division modulus of N+δN can be achieved. A ΔΣ modulator 211 is provided that receives a desired channel value, and generates therefrom appropriate values for N and M. In the exemplary embodiment, a first-order ΔΣ modulator is shown, but this is not essential.
The ΔΣ noise will be suppressed by the loop response (i.e., if the loop bandwidth is not too wide), but to avoid spurious tones due to ΔΣ-modulator limit cycles (i.e., a repetitive behavior associated with having a period time that is too short), extra noise (“dither”) is typically added to further randomize the ΔΣ noise. This is modeled in FIG. 3 by the summing circuits 213 that adds a dither value to the ΔΣ noise. The resultant value is then quantized, which adds its own quantization noise, eq(k). The resultant value M, which is generated at the output of the ΔΣ modulator 211, is supplied to one of the modulus inputs of the frequency divider 205.
To make the noise shaping possible, the divider modulus should not be chosen to be only the two closest integer factors, but should instead be varied between, for example, N−M, . . . , N+M. This extra modulus range is required if noise is to be pushed out in frequency, away from the VCO carrier; otherwise, the loop filter will not be able to suppress the ΔΣ noise. As a consequence of this extended divider modulus range, the instantaneous phase error will be increased. The ΔΣ-loop equations then become:                                           i            e                    =                                    K              P                        ⁡                          (                                                ϕ                  R                                -                                                      ϕ                    o                                                        N                    +                                          δ                      ⁢                                                                                          ⁢                      N                                                                      +                                  N                  ΔΣ                                            )                                      ⁢                                  ⁢                                            ϕ              o                        =                                          i                e                            ⁢                              Z                ⁡                                  (                  s                  )                                            ⁢                                                K                  V                                s                                              ,                                    (        2        )            where N+δN and NΔΣ represent the fractional division ratio and the ΔΣ-modulator noise, respectively. FIG. 4 is a graph that illustrates the output spectrum of the frequency divider 205.
FIG. 5 is a block diagram of a typical embodiment of the conventional phase detector 201. The use of first and second digital latches 501, 503 enables multiple states (not shown in FIG. 5) and, hence, an extended range of the phase detector 201. In operation, the first latch 501 controls whether a first charge pump 505 is on or off. Similarly, the second latch 503 controls whether the second charge pump 507 is on or off. The first and second charge pumps 505, 507 are connected in series, with the phase detector output current, ie, being supplied at the connection point between the two charge pumps. The amount of phase detector output current, ie, is related to whether none, one, or both of the first and second charge pumps 505, 507 are turned on. The amount of time that ie is one-zero is a function of the phase difference between the two input signals, φa and φb. Each of these signals is supplied to a clock input of a respective one of the first and second latches 501, 503. The first of these signals to present a clocking edge causes the output of the corresponding latch to be asserted, which in turn, causes a corresponding one of the first and second charge pumps 505, 507 to turn on. When the clocking edge of the remaining input signal is subsequently asserted, it too causes the output of its corresponding latch to be asserted. The outputs of both the first and second latches 501, 503 are further supplied to respective inputs of a logical AND gate 509, whose output is supplied to the RESET inputs of both the first and second latches 501, 503. Consequently, when the outputs of both latches 501, 503 are asserted, the output of the AND gate 509 will be asserted as well, thereby resetting both latches 501, 503. They are now initialized to repeat the process again for a next cycle. As a result, the output current ie is either a positive value (being supplied by the first charge pump 505) if the first input signal φa leads the second input signal φb, or else it is a negative value (being drawn by the second charge pump 507) if the second input signal φb leads the first input signal φa.
A typical phase-detector transfer function is depicted in FIG. 6, in which the average phase detector output current, ie—avg, is plotted as a function of phase difference, Δφ. Not shown in FIG. 6 is a “dead-zone” that would be associated with the phase detector depicted in FIG. 5. The dead-zone, and ways of dealing with it, are discussed in greater detail below.
The phase detector output is often designed with charge pumps having a high-impedance off state. This high-impedance off state effectively turns the loop filter into an integrator (i.e., if the trans-impedance Z(s) is capacitive). A simplified rendition of a charge pump tat may be used as either of the charge pumps 505, 507 is shown in FIG. 7. In this simplified design, the current for the “down” stage is drawn by transistor 707 when the “down” signal 709 is asserted. The current for the “up” stage is supplied by the current mirror arrangement of transistors 701, 703 and 705 when the “up” signal 711 is asserted.
Referring back to FIGS. 3 and 5, when the PLL 201 is properly tracking its reference, φR, both of the phase-detector latches 501, 503 trigger almost simultaneously, due to the fact that the phase difference between the two input signals becomes very small. The reset signal immediately resets the first and second latches 501, 503 and, as a consequence, only short spikes appear at the latch outputs, too fast to turn on the respective first and second charge pumps 505, 507.
In fact, even when there is a small phase error (i.e., a tracking error), the first and second latches 501, 503 will reset too fast for the charge pumps 505, 507 to react. Consequently, the phase-detector transfer function will be characterized by a small dead-band (low-gain region) around the origin. A common technique to combat this dead-band is to utilize a delay circuit 801, which adds a delay δT to the reset signal, as illustrated in FIG. 8. With this extra delay, the up and down pulses will each be long enough to activate the charge pumps, thereby eliminating the dead-band.
Despite the use of the delay circuit 801 as described above, the ΔΣ-based fractional-N PLLs reported in the literature often have inferior noise performance compared to their integer-divide counterparts. This has prevented their use in demanding applications, like cellular phones. The origin of this excess noise has conventionally been attributed to the ΔΣ-modulator noise, even though, as shown in FIG. 2, the noise can be made to fall outside the loop bandwidth.
Consequently, it is desirable to provide components and techniques for improving the noise performance of fractional-N PLLs.